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Defect Investigation by Atomic-Resolution STEM of III-V Horizontal Nanowires grown via Template-Assisted Selective area Epitaxy

Abstract number: 6364

Session Code: MS03-677

DOI: 10.1002/9783527808465.EMC2016.6364

Meeting: The 16th European Microscopy Congress 2016

Session: Materials Science

Topic: Semiconductors and devices

Presentation Form: Poster

Corresponding Email: nicolas.bologna@empa.ch

Nicolas Bologna (1, 2, 3), Moritz Knoedler (2, 3), Mattias Borg (4, 2), Davide Cutaia (2), Rolf Erni (1), Heike Riel (2), Marta Rossel D. (1, 2)

1. Electron Microscopy Center, Empa, Dubendorf, Suisse 2. M.I.N.D., IBM ZRL, Ruschlikon, Suisse 3. Laboratoire des Matériaux Semiconducteurs, EPFL, Lausanne, Suisse 4. Electrical and Information Technology, Lund University, Lund, Suède

Keywords: dislocations, EDX, GPA, III-V Nanowires, stacking faults, STEM

Scaling of silicon microelectronics is reaching fundamental physical limitations related in particular to the power consumption. A possible solution is represented by III-V semiconductors integrated on Si which have much higher electron mobility and injection velocity. The possibility to grow III-V nan-owires allows also the creation of new transistor concepts for Tunnel Field-Effect Transistors [1], which could lead to an increase in the efficiency of the circuits by reducing the supply voltage and thus the power consumption.
The growth of III-V nanowires by Template Assisted Selective Epitaxy (TASE) (Fig. 1a) [2] has enabled the direct integration of heterostructures on Si (100) for TFET applications. The performance of the de-vice may however be affected by the presence of defects (twins, dislocations, stacking faults, anti-phase boundaries) along the nanowire since every single discontinuity in the crystal can lead to a mod-ification in the electrical properties of the material. The understanding, control and suppression of such defects have always been a very challenging task and a crucial point to obtain well performing devices.
Here, we report the investigation of different III-V compounds, by means of atomic-resolution STEM, starting from GaAs homostructures to InAs-GaSb heterostructures (Fig.1b), allowing detailed charac-terization of defects, strains and compositions. We make use of the large degree of freedom of growth parameters in the TASE technique (temperature, V/III ratio, molar flux of precursors) to prepare nan-owire samples (Fig.1b) with the aim to find the right parameters combination to reduce the defects density. Our analysis confirms a process-dependent defect density in nanowires and shows that de-fect-free nanowires can be indeed obtained by optimizing the growth conditions (Fig.2).

[1]. Riel, H., Wernersson, L.-E., Hong, M. & del Alamo, J. a. III–V compound semiconductor transistors—from planar to nanowire structures. MRS Bull. 39, 668–677 (2014)
[2]. Schmid, H. et al. Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous inte-gration with Si. Appl. Phys. Lett. 106, 233101 (2015).

Acknowledgments: This work was supported by the Swiss National Science Foundation (project no. 200021_156746) and E2SWITCH (project no. 619509).

Figures:

Fig.1 (a) Graphical representation of the TASE technique

(b) BF image of InAs-GaSb interface highlighted by EDX map.

Fig.2 HAADF-STEM images of GaAs nanowires (a) with planar defects

and (b) without defects

To cite this abstract:

Nicolas Bologna, Moritz Knoedler, Mattias Borg, Davide Cutaia, Rolf Erni, Heike Riel, Marta Rossel D.; Defect Investigation by Atomic-Resolution STEM of III-V Horizontal Nanowires grown via Template-Assisted Selective area Epitaxy. The 16th European Microscopy Congress, Lyon, France. https://emc-proceedings.com/abstract/defect-investigation-by-atomic-resolution-stem-of-iii-v-horizontal-nanowires-grown-via-template-assisted-selective-area-epitaxy/. Accessed: December 4, 2023
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