The semiconductor industry is a dynamic, rapidly growing manufacturing sector. In 2015, global sales of semiconductor products increased 9.9% and reached a record US $335.8 billion [1]. Constantly evolving microelectronic device designs continue to grow more complex, more compact, and smaller. For example, three-dimensional (3D) NAND flash memory cells are layered vertically in three-dimensional stacks, which provides much greater cell density and increases memory capacity [2]. Such design complexity makes maintaining manufacturing quality standards a consistent challenge for the industry and failure analysis plays a critical role in meeting that challenge. Failure analysis can determine the root cause of a defective device; it enables failure identification and characterization, as well as provides feedback for product and process improvement. Many failure analysis techniques, both nondestructive and destructive, have been developed in the past five decades [3, 4]:

·         nondestructive techniques: electrical measurement and testing, infrared and X-ray examination, and optical or electron microscopy evaluation

·         destructive techniques: chemical etching, mechanical polishing, plasma etching, and delayering

Many techniques are untenable for multilayer devices. For example, Samsung found that etching agents are too aggressive and the company enumerated several major structural failures that can occur in NAND flash memory related to etching or particle contamination. Delayering is a popular choice because it allows top-down, whole chip characterization. However, delayering 3D devices with multiple layers is difficult. The main challenge presented by a vertical stack is looking through a stack of many dissimilar layers. Instrumentation that employs low energy, broad beam, argon ion milling using a top-down delayering technique can help to expose a defect region for further analysis [5]. The work presented is a new development in semiconductor device delayering for failure analysis using low energy, broad-beam argon ion milling. 

References

1. Rosso, D. (2016, February 1). Semiconductor Industry Association – Global semiconductor sales top $335 billion in 2015. Retrieved from http://www.semiconductors.org/news/2016/
   02/01/global_sales_report_2015/global_semiconductor_sales_top_335_billion_in_2015.
2. Shimpi, A. L. (2013, August 21). Samsung’s V-NAND: Hitting the reset button on NAND scaling. Retrieved from http://www.anandtech.com/show/7237/samsungs-vnand-hitting-the-reset-button-on-nand-scaling.
3. Lakshminarayanan, V. (2001). Failure analysis techniques for semiconductors and other devices. Retrieved from Mobile Dev & Design website: http://mobiledevdesign.com/news/
   failure-analysis-techniques-semiconductors-and-other-devices.
4. Crockett, A., Almoustafa, M., & Vanderlinde, W. (2004). Plasma delayering of integrated circuits. Microelectronics Failure Analysis Desk Reference, 4, 243-25. 

Figures:

Figure 1. Cross-section sample of 3D NAND flash memory channels.

Figure 2. Two different layers of 3D NAND flash memory as imaged during the top-down delayering process using low energy, broad-beam argon ion milling.

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EMC Abstracts - https://emc-proceedings.com/abstract/precision-top-down-delayering-of-microelectronics-devices-using-broad-beam-argon-ion-milling/